TITLE "dad"; FUNCTION lpm_counter (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, updown, aclr, aset, aconst, aload, sclr, sset, sconst, sload) WITH (LPM_WIDTH, LPM_DIRECTION, LPM_MODULUS, LPM_AVALUE, LPM_SVALUE, CARRY_CNT_EN, LABWIDE_SCLR) RETURNS (q[LPM_WIDTH-1..0], eq[9..0]); FUNCTION lpm_mux (data[LPM_SIZE-1..0][LPM_WIDTH-1..0], sel[LPM_WIDTHS-1..0], clock, aclr) WITH (LPM_WIDTH, LPM_SIZE, LPM_WIDTHS, LPM_PIPELINE) RETURNS (result[LPM_WIDTH-1..0]); FUNCTION lpm_ff (data[LPM_WIDTH-1..0], clock, enable, sclr, sset, sload, aclr, aset, aload) WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE, LPM_FFTYPE) RETURNS (q[LPM_WIDTH-1..0]); SUBDESIGN dad ( hf_spare : INPUT; dad_spare : INPUT; a : INPUT; % clock for data stream 1 % bb[4..0] : OUTPUT; % !(the "a" clock with f/2) (five identical) % in[22..0] : INPUT; % data stream 1: [0]=data_valid_signal,[20..1]=data,[21]=error,[22]=unused_sync_detect % ooo[47..0] : OUTPUT; % output-data stream 1 % a_ : INPUT; % clock for data stream 2 % in_[22..0] : INPUT; % data stream 2: [0]=data_valid_signal,[20..1]=data,[21]=error,[22]=unused_sync_detect % ooo_[47..0] : OUTPUT; % output-data stream 2 % reset : INPUT; mdv : OUTPUT; % the AND of all data valid outputs % dvab : OUTPUT; % the AND of link#1 dv outputs % dvcd : OUTPUT; % the AND of link#2 dv outputs % merr : OUTPUT; % the OR of all error outputs % errab : OUTPUT; % the OR of link#1 error outputs % errcd : OUTPUT; % the OR of link#2 error outputs % ) VARIABLE c : DFF; c1 : DFF; out :lpm_counter WITH (LPM_WIDTH=4,LPM_MODULUS=10); % write counter 1 % out_ :lpm_counter WITH (LPM_WIDTH=4,LPM_MODULUS=10); % write counter 2 % out1 :lpm_counter WITH (LPM_WIDTH=3,LPM_MODULUS=5); % read counter % muxx :lpm_mux WITH (LPM_WIDTH=44,LPM_SIZE=5,LPM_WIDTHS=3); muxx_ :lpm_mux WITH (LPM_WIDTH=44,LPM_SIZE=5,LPM_WIDTHS=3); reeg0:lpm_ff WITH (LPM_WIDTH=22); reeg1:lpm_ff WITH (LPM_WIDTH=22); reeg2:lpm_ff WITH (LPM_WIDTH=22); reeg3:lpm_ff WITH (LPM_WIDTH=22); reeg4:lpm_ff WITH (LPM_WIDTH=22); reeg5:lpm_ff WITH (LPM_WIDTH=22); reeg6:lpm_ff WITH (LPM_WIDTH=22); reeg7:lpm_ff WITH (LPM_WIDTH=22); reeg8:lpm_ff WITH (LPM_WIDTH=22); reeg9:lpm_ff WITH (LPM_WIDTH=22); reeg0_:lpm_ff WITH (LPM_WIDTH=22); reeg1_:lpm_ff WITH (LPM_WIDTH=22); reeg2_:lpm_ff WITH (LPM_WIDTH=22); reeg3_:lpm_ff WITH (LPM_WIDTH=22); reeg4_:lpm_ff WITH (LPM_WIDTH=22); reeg5_:lpm_ff WITH (LPM_WIDTH=22); reeg6_:lpm_ff WITH (LPM_WIDTH=22); reeg7_:lpm_ff WITH (LPM_WIDTH=22); reeg8_:lpm_ff WITH (LPM_WIDTH=22); reeg9_:lpm_ff WITH (LPM_WIDTH=22); regf:lpm_ff WITH (LPM_WIDTH=48); regf_:lpm_ff WITH (LPM_WIDTH=48); if1 : NODE; en : NODE; en_ : NODE; oo[2..0] : NODE; b : NODE; misc:lpm_ff WITH (LPM_WIDTH=6); BEGIN en = !in[0]#ooo[0]#ooo_[0]; en_ = !in_[0]#ooo[0]#ooo_[0]; c.clk =a; % generate the f/2 clock % c.prn =VCC; c.clrn =VCC; c.d =!c.q; b =c.q; % this is the f/2 clock % out.aclr =!en; % start the write counter 1 % out.clk_en =en; out.clock =a; out_.aclr =!en_; % start the write counter 2 % out_.clk_en =en_; out_.clock =a_; IF out.q[]==H"5" THEN if1=VCC; % when the write counter 1 reaches "5", % ELSE if1=GND; % the signal if1 gets H % END IF; c1.clk =if1; % and it is latched with c1 % c1.PRN =VCC; c1.d =VCC; c1.clrn =en; % then % out1.aclr =!en; % the read counter starts % out1.clk_en =c1.q; out1.clock =c.q; oo[2..0] =out1.q[]; % and commands the multiplexers % reeg0.data[]=in[21..0]; reeg0.clock=a; reeg0.enable=out.eq[0]; reeg1.data[]=in[21..0]; reeg1.clock=a; reeg1.enable=out.eq[1]; reeg2.data[]=in[21..0]; reeg2.clock=a; reeg2.enable=out.eq[2]; reeg3.data[]=in[21..0]; reeg3.clock=a; reeg3.enable=out.eq[3]; reeg4.data[]=in[21..0]; reeg4.clock=a; reeg4.enable=out.eq[4]; reeg5.data[]=in[21..0]; reeg5.clock=a; reeg5.enable=out.eq[5]; reeg6.data[]=in[21..0]; reeg6.clock=a; reeg6.enable=out.eq[6]; reeg7.data[]=in[21..0]; reeg7.clock=a; reeg7.enable=out.eq[7]; reeg8.data[]=in[21..0]; reeg8.clock=a; reeg8.enable=out.eq[8]; reeg9.data[]=in[21..0]; reeg9.clock=a; reeg9.enable=out.eq[9]; reeg0_.data[]=in_[21..0]; reeg0_.clock=a_; reeg0_.enable=out_.eq[0]; reeg1_.data[]=in_[21..0]; reeg1_.clock=a_; reeg1_.enable=out_.eq[1]; reeg2_.data[]=in_[21..0]; reeg2_.clock=a_; reeg2_.enable=out_.eq[2]; reeg3_.data[]=in_[21..0]; reeg3_.clock=a_; reeg3_.enable=out_.eq[3]; reeg4_.data[]=in_[21..0]; reeg4_.clock=a_; reeg4_.enable=out_.eq[4]; reeg5_.data[]=in_[21..0]; reeg5_.clock=a_; reeg5_.enable=out_.eq[5]; reeg6_.data[]=in_[21..0]; reeg6_.clock=a_; reeg6_.enable=out_.eq[6]; reeg7_.data[]=in_[21..0]; reeg7_.clock=a_; reeg7_.enable=out_.eq[7]; reeg8_.data[]=in_[21..0]; reeg8_.clock=a_; reeg8_.enable=out_.eq[8]; reeg9_.data[]=in_[21..0]; reeg9_.clock=a_; reeg9_.enable=out_.eq[9]; muxx.data[0][21..0]=reeg1.q[]; muxx.data[0][43..22]=reeg0.q[]; muxx.data[1][21..0]=reeg3.q[]; muxx.data[1][43..22]=reeg2.q[]; muxx.data[2][21..0]=reeg5.q[]; muxx.data[2][43..22]=reeg4.q[]; muxx.data[3][21..0]=reeg7.q[]; muxx.data[3][43..22]=reeg6.q[]; muxx.data[4][21..0]=reeg9.q[]; muxx.data[4][43..22]=reeg8.q[]; muxx_.data[0][21..0]=reeg1_.q[]; muxx_.data[0][43..22]=reeg0_.q[]; muxx_.data[1][21..0]=reeg3_.q[]; muxx_.data[1][43..22]=reeg2_.q[]; muxx_.data[2][21..0]=reeg5_.q[]; muxx_.data[2][43..22]=reeg4_.q[]; muxx_.data[3][21..0]=reeg7_.q[]; muxx_.data[3][43..22]=reeg6_.q[]; muxx_.data[4][21..0]=reeg9_.q[]; muxx_.data[4][43..22]=reeg8_.q[]; muxx.sel[] =oo[]; regf.data[0]=!muxx.result[0]; regf.data[21..1]=muxx.result[21..1]; regf.data[23..22]=GND; regf.data[24]=!muxx.result[22]; regf.data[45..25]=muxx.result[43..23]; regf.data[47..46]=GND; regf.clock =b; regf.enable =VCC; ooo[] =regf.q[]; regf.sclr =!c1.q; muxx_.sel[] =oo[]; regf_.data[0]=!muxx_.result[0]; regf_.data[21..1]=muxx_.result[21..1]; regf_.data[23..22]=GND; regf_.data[24]=!muxx_.result[22]; regf_.data[45..25]=muxx_.result[43..23]; regf_.data[47..46]=GND; regf_.clock =b; regf_.enable =VCC; ooo_[] =regf_.q[]; regf_.sclr =!c1.q; bb[] =!b; misc.data[0]=!muxx.result[0]&!muxx.result[22]&!muxx_.result[0]&!muxx_.result[22]; misc.data[1]=!muxx.result[0]&!muxx.result[22]; misc.data[2]=!muxx_.result[0]&!muxx_.result[22]; misc.data[3]=muxx.result[21]&muxx.result[43]&muxx_.result[21]&muxx_.result[43]; misc.data[4]=muxx.result[21]&muxx.result[43]; misc.data[5]=muxx_.result[21]&muxx_.result[43]; misc.clock=b; misc.enable=c1.q; mdv =misc.q[0]; dvab =misc.q[1]; dvcd =misc.q[2]; merr =misc.q[3]; errab =misc.q[4]; errcd =misc.q[5]; END;